What
are the key factors that contribute to
missed commitments for analog IP?
-
Deliverable and receivable expectations not
matched. Someone downstream did not receive what they needed for
successfully completing their tasks.
-
Undefined or under-defined deliverable
details (design and
non-
design).
-
Detail lacking in the IP requirements,
leading to rework of completed work.
A
lack in clarity in individual objectives for the IP is the culprit
here; a clarity that can be improved through guidance in detailed
planning and
documentation to drive that plan. How does
your analog IP documentation stack up in the area of creating clarity
of individual objectives?
Is your analog IP
block level documentation:
-
creating alignment of objectives for all
analog
design activities for your chip?
-
servicing the entire new product
development teams objective needs for both design and non design
participants?
-
enabling the team to execute their goals in
a
predictable fashion?
-
clearly passing the IP level requirements
from the chip architect to the
transistor level designer?
-
serving the documentation
requirements for reuse?
-
acting as the key document to guide
consistent design
review content?
If your current
documentation strategy is not
providing these essential benefits please read on
about an analog block design guide template that will achieve these
objectives, plus many more. It's on the shelf
and ready for your final customization. Sound valuable? Please read
on...
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Analog
Block Design Guide Template
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Benefits
to your Development Team
- Enables predictable design execution for
analog IP.
- Provides clarity of individual objectives.
- Alignment of the design team to test,
product
engineering, applications and business expectations.
Drives a consistent, predefined and predictable
design process.
- Provides design process flow and
documentation
for each analog IP block, from concept through silicon validation.
- Includes the information to enable
reuse... no
extra documentation work necessary.
- Guides consistent analog IP block design
reviews.
About this Analog Block Guide Template
Offer
- Lowest
level document in the family of design
guides.
- Foundation of an organizations transistor
level
design process.
- Starter document covering generic
deliverables
for most aspects of an analog block.
- Will require customization for your
design
process, business process and design best practices. Anticipate
template is ~90% complete for your process.
- We can customize with your team for an
additional
fee.
- In Microsoft Word Format.
No Risk
Offer!
- Full refund If not 100% satisfied with
the template. Must request refund within one week of download.
- Includes two weeks of phone/email support
for
customization questions.
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Analog block guide covers a broad landscape
of design managed activities:
- Early stage feasibility, risk mitigation
and
partitioning activities
- Transistor design simulation and
validation activities
- Comprehensive enough to guide analog
block design
reviews
The activities
are partitioned within 5 main sections of the analog block guide:
- opportunity assessment
- architecture
- transistor design
- Integration
- Silicon validation
The analog
block guide content addresses multiple disciplines:
- Product
Engineering
- Test Engineering
- Applications and Systems
- Design
- The
analog block design guide template described here covers the lowest
level of abstraction (transistor) as seen in the diagram above
- Template is used to create a guide for
each lower level analog IP block.
- Facilitates proper communication of
requirements from chip architect to transistor designer
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- Analog
requirements section completed by chip architect for each analog IP
block guide
- Information is shared down through the
hierarchy,
not duplicated
With
a design teams limited ability to commit resources for process
improvements this template represents a bargain for opening the door to
a more predictable design process. With
this
no
risk offer why not download the analog block design
guide template today!
Interested in customized design guides for the system, chip or block/IP
level?
Contact me via email or
phone 480-442-6730 to discuss your specific requirements.
Sincerely,
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Jeff
Jorvig
The IC Coach
www.jorvigconsulting.com
"Providing solutions to the
systemic
project barriers that impact new product revenue objectives."
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