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Dear Product Development Professional,
What factors contribute to schedule slips?
Task deliverable and receivable expectations not
matched. Someone did not get what they expected.
Undefined or under-defined task details (design and
non-
design)
Detail lacking in the requirements (similar to
deliverables but referring to electrical/functional information)
Documentation is the culprit here, an engineers favorite task. These
factors
can't be pinned on design tools or design flow but
they certainly can be pinned on planning and the
documentation that captures the plan(s). How does
your block level documentation stack up?
Is your analog block level documentation:
creating alignment of objectives for all analog block
design activities in your chip?
servicing the entire new product
development teams needs beyond design?
enabling the team to execute their goals in a
predictable fashion?
clearly passing the
block level requirements from the chip architect to the
transistor level designer?
serving the documentation
requirements for reuse?
acting as the key document to guide consistent design
reviews?
If your current documentation strategy is not
providing these essential benefits please read on
about an analog block design guide template that will pave a
path
towards achieving these objectives, plus many more. It's on the shelf
and ready for your final customization. Sound interesting?
If so, please read on... |
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With
a design teams limited ability to commit resources for process
improvements this template represents a bargain for opening the door to
a more predictable design process. With this no risk offer why not
order the analog block design guide template today!
Interested in customized design guides?
Contact us via email or
480-895-0478 to discuss your specific requirements.
Best
Regards,
Jeff Jorvig
Jorvig Consulting, Inc.
phone:
480-895-0478
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